1. Technical Field
The present disclosure relates to semiconductor memory devices, and in particular, to a data path circuit for a semiconductor memory device, such as a dynamic random access memory (DRAM), or the like.
2. Discussion of the Related Art
A DRAM which is often used as a main memory in an electronic system has a high operating speed and is highly integrated according to the users' demands.
Such a DRAM is a volatile memory which has a plurality of memory cells, each typically including one access transistor and one storage capacitor. The DRAM has a refresh operation as well as a read/write operation.
High-performance DRAMs with an improved operating speed, such as the Synchronous DRAM (SDRAM), the Double Data Rate (DDR) SDRAM, the Fast Cycle RAM (FCRAM), and the like, have been developed at present. Of these, the SDRAM is configured such that data input/output is possible at either the rising edge or the falling edge of the clock. On the other hand, the DDR SDRAM is configured such that data input/output is possible at the rising edge and the falling edge of the clock, so the DDR SDRAM has a data transmission speed two times higher than that of the SDRAM. Further, the DDR SDRAM includes a data input/output pin, e.g., a Data Input/Output Masking (DQM) Pin, for masking data undesired to be written when a data write command is generated. When a data masking signal is activated, data input/output is disabled in accordance with predetermined latency.
The data masking operation which is widely used in the DDR type DRAM is performed by a Data Masking (DM) circuit which enables a data masking control signal in response to a write inhibition signal input from the outside through a DM pin. In this case, write data is not supplied to a memory cell into which it is undesired to write data, so the data masking operation is realized.
During the data masking operation mode while the write operation is being executed, the electric charges on the global input/output lines may be applied to the bit line connected to the relevant memory cell, which can cause bit line disturbance. The bit line disturbance can cause data stored in advance in the selected memory cell to be affected, such that a read error can occur during the data read operation.
Accordingly, there is a need for a technique for minimizing or eliminating such bit line disturbance during the data masking operation mode while the write operation is being executed.